Multiphase signal generators are provided for generating a plurality of output phases. They are widely used in many communication systems and devices, e.g. in phase locked loops, clock and data recovery systems, receivers and high-speed serial data links.
In particular multi-Gigabit receivers of high-speed serial links demand for highly precise clock generation. High-speed serial links are used to transmit data from chip to chip over wired media, such as a printed circuit board or a backplane. The aggregate data rates in future chip to chip communication will soon reach several Tbits/s in some applications. Since serial links are analog in nature, ordinary scaling in power and area, as seen for digital logic, does not apply. Hence, the relative area and power consumption of the chip input/output interface versus logic is increasing. On the receiver side, most power is spent for clock generation. In consequence, it is a challenge to find serial link receiver architectures which minimizes area and power consumption.
In high-speed links, sub-rate receiver architectures are frequently used. This allows clocking the receiver at an integer fraction 1/S of the data rate, thereby relaxing the requirements on the sampling latches and the clock distribution circuitry. Thus, sub-rate receivers allow exploring the speed limits of a given technology and reducing the power consumption.
Typical values for S range between 2 and 8. One solution for highly precise clock generation is an adjustable phase locked loop (PLL) comprising a multiphase signal generator.
Such an adjustable phase locked loop is described in “Thomas Toifl, Christian Menolfi, Peter Buchmann, Marcel Kossel, Thomas Morf, Robert Reutemann, Michael Ruegg, Martin L. Schmatz, Jonas Weiss, A 0.94-ps-RMS-Jitter 0.016-mm2 2.5-GHz Multiphase Generator PLL with 360 Digitally Programmable Phase Shift for 10-Gb/s Serial Links, IEEE JOURNAL OF SOLID STATE CIRCUITS, Vol. 40, No. 12, DECEMBER 2005.
It is an object of the invention to provide an improved multiphase signal generator. A further object is to provide a phase locked loop, a clock and data recovery system and a receiver with enhanced data signal quality. A further object is to provide a phase locked loop, a clock and data recovery system and a receiver with reduced chip area and power consumption.